The present invention generally relates to semiconductor devices, and more particularly relates to semiconductor devices having a silicon germanium channel.
One promising dual channel CMOS integration scheme for future technologies utilizes tensile-strained silicon (Si) for n-type Field Effect Transistors (nFETs) and compressively strained silicon germanium (SiGe) grown on a Si substrate for p-type Field Effect Transistors (pFETs). With respect to pFETs, a strained SiGe channel with a high germanium (Ge) content is usually required for achieving increased device performance and reliability. However, it is difficult to achieve these advantages for pFETs having a strained SiGe channel comprising high germanium (Ge) content using conventional fabrication techniques.